Fabrication of p-n Junction
Fabrication of p-n junction:
Thermal Oxidation: Thermal oxidation is a technique that uses high temperature (700- 1300oC) for growing the layer of silicon dioxide (SiO2) on the substrate silicon. In thermal oxidation, silicon substrate is exposed to an oxidizing environment of O2 or H2O at elevated temperature, producing oxide films whose thicknesses range from 60 to 10000 Ao. Silicon has a natural inclination to form a stable oxide even at room temperature, as long as an oxidizing ambient is present. The elevated temperature used in thermal oxidation therefore serves primarily as an accelerator of the oxidation process, resulting in thicker oxide layers per unit of time.
Thermal oxidation is accomplished using an oxidation furnace or diffusion furnace, since oxidation is basically a diffusion process involving oxidant species. A furnace typically consists of: 1) a cabinet; 2) a heating system; 3) a temperature measurement and control system; 4) fused quartz process tubes where the wafers undergo oxidation; 5) a system for moving process gases into and out of the process tubes; and 6) a loading station used for loading (or unloading) wafers into (or from) the process tubes.
If the oxidation is done for long time, the rate of oxide formation is given by the Parabolic Growth Law: xo2 = B t, where xo is the thickness of the growing oxide, B is the parabolic rate constant, and t is the oxidation time. This shows that the oxide thickness grown is proportional to the square root of the oxidizing time, which means that the oxide growth is hampered as the oxide thickness increases. If the oxidation is done for short durations, its rate is given by the Linear Growth Law: xo = C (t + t), where xo is the thickness of the growing oxide, C is the linear rate constant, t is the oxidation time, and t is the initial time displacement to account for the formation of the initial oxide layer at the start of the oxidation process.
Oxide growth rate is accelerated by an increase in oxidation time, oxidation temperature, or oxidation pressure. The crystallographic orientation of the wafer; its doping level; the presence of halogen impurities and the presence of a photon flux affects the growth of oxide. The density of silicon oxide is ~2.3 gm/cc, its dielectric constant is 3.9, its refractive index is 1.5 and its breakdown field is 107 volts/cm. Oxide is used as gate material, as insulator / spacer, as implantation barrier and as device sealant.
Diffusion:
Thermal Oxidation: Thermal oxidation is a technique that uses high temperature (700- 1300oC) for growing the layer of silicon dioxide (SiO2) on the substrate silicon. In thermal oxidation, silicon substrate is exposed to an oxidizing environment of O2 or H2O at elevated temperature, producing oxide films whose thicknesses range from 60 to 10000 Ao. Silicon has a natural inclination to form a stable oxide even at room temperature, as long as an oxidizing ambient is present. The elevated temperature used in thermal oxidation therefore serves primarily as an accelerator of the oxidation process, resulting in thicker oxide layers per unit of time.
Thermal oxidation is accomplished using an oxidation furnace or diffusion furnace, since oxidation is basically a diffusion process involving oxidant species. A furnace typically consists of: 1) a cabinet; 2) a heating system; 3) a temperature measurement and control system; 4) fused quartz process tubes where the wafers undergo oxidation; 5) a system for moving process gases into and out of the process tubes; and 6) a loading station used for loading (or unloading) wafers into (or from) the process tubes.
If the oxidation is done for long time, the rate of oxide formation is given by the Parabolic Growth Law: xo2 = B t, where xo is the thickness of the growing oxide, B is the parabolic rate constant, and t is the oxidation time. This shows that the oxide thickness grown is proportional to the square root of the oxidizing time, which means that the oxide growth is hampered as the oxide thickness increases. If the oxidation is done for short durations, its rate is given by the Linear Growth Law: xo = C (t + t), where xo is the thickness of the growing oxide, C is the linear rate constant, t is the oxidation time, and t is the initial time displacement to account for the formation of the initial oxide layer at the start of the oxidation process.
Oxide growth rate is accelerated by an increase in oxidation time, oxidation temperature, or oxidation pressure. The crystallographic orientation of the wafer; its doping level; the presence of halogen impurities and the presence of a photon flux affects the growth of oxide. The density of silicon oxide is ~2.3 gm/cc, its dielectric constant is 3.9, its refractive index is 1.5 and its breakdown field is 107 volts/cm. Oxide is used as gate material, as insulator / spacer, as implantation barrier and as device sealant.
Diffusion:
Any gradient of concentration forces the movement of species from higher
concentration region to lower concentration region. This process is called diffusion and it
has been used in the fabrication of semiconductor devices to move impurity atoms in the
semiconductor substrate. The diffusivity of different dopant species depends upon the
diffusing atom and the host material. Diffusion is used to introduce dopant atoms into
silicon from a chemical vapor source and also to anneal the crystal defects after ion
implantation.
Increasing temperature enhances the rate of diffusion; the diffusion time and temperature
determine the depth of dopant penetration. Diffusion is used to form the source, drain,
and channel regions in a MOS transistor. But diffusion can also cause unwanted parasitic
effect, because it takes place during all high temperature process steps.Because of the
undesirable and unpredictable diffusion phenomena, modern process technologies have
reduced the role of diffusion by decreasing the thermal budget. This is done by reducing
the process temperature or by performing short term annealing processes at high
temperatures.
Ion implantation: It is one of the two approaches of selectively introducing the dopants
in the substrate. The process of diffusion done at ~1000oC can send dopants in bare
silicon. However, ion implantation is a major improvement over diffusion as it executes
this task more precisely, and efficiently. The implantation is done at room temperature.
Implanter generates ion beam in the energy range 2 KeV–2 MeV, impinges them in the
substrate so that the ions come to rest beneath the surface. Typical range of implantation
dose is 1012–1018 ions/cm2. The ions reach a depth of 100 Å-10 micron. Implantation
offers:
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Precise control of dopant density
-
Sends dopants through oxide too
-
Introduces dopants that may not be diffused
Boron, Arsenic and Phosphorous are frequently implanted species. In, Sb, Ge, Si, N, He and H are also implanted. Fabrication of a simple NMOS may need few implants but modern CMOS with embedded memory may need over 30 implants. Ion energy and angle of incidence determine the penetration depth and ion current (dose) determines the implantation time. A post-implant annealing is done at 900–1,100°C to repair the crystal damage caused by ion implantation. Most implantation systems consist of: Ion source, Ion extraction mechanism, Ion accelerator and Ion beam manipulator. Positively charged ion beam can create E fields (x00 volts) on wafer. It is neutralized with electric charge of opposite polarity using one of the several kinds of ion beam neutralizer.
RF Plasma Cell: An e– beam source is positioned upstream. It confines high energy e– with a mag field and allows lower energy e– to drift along the ion beam
An ion beam neutralizer: Energetic e– are directed to an ionizable gas, producing low energy electrons, which are trapped by a positively charged ion beam.
Plasma Shower: In the vicinity of sample surface, plasma ionizes a gas and irradiates
electrons on the sample surface.
Plasma Flood: Plasma with low energy e– magnetically confined into the ion beam Electron Shower: low energy e– are entrapped within the +ve ion beam
Chemical vapor deposition: It is a chemical process us
exposed to volatile precursors such as SiH2Cl2, carried with an inert gas. The precursor gases react on the substrate surface and creating the deposition of the desired film. CVD is used to deposit monocrystalline, polycrystalline, amorphous,
and epitaxial films of polysilicon, single crystal silicon, SiO2, silicon nitride etc.
Plasma Flood: Plasma with low energy e– magnetically confined into the ion beam Electron Shower: low energy e– are entrapped within the +ve ion beam
Chemical vapor deposition: It is a chemical process us
exposed to volatile precursors such as SiH2Cl2, carried with an inert gas. The precursor gases react on the substrate surface and creating the deposition of the desired film. CVD is used to deposit monocrystalline, polycrystalline, amorphous,
and epitaxial films of polysilicon, single crystal silicon, SiO2, silicon nitride etc.
performance, uniform coatings of metals or polymers, even on contoured surfaces. In this
ed to produce high quality, high-process, the substrate is
A mixture of pure hydrogen (H2) and silane (SiH4) or dichlorosilane (SiH2Cl2) or silicon
tetrachloride (SiCl4) is sent as precursor to the CVD system having silicon are at 1000 °C
and low pressure. The reaction of the gases at the surface of Si, occurring in two steps
leads to a deposition of a fresh layer of silicon as follows.
SiCl4 + H2→SiCl2 + 2HCl ; 2 SiCl2→Si + SiCl4
The deposited layer may inherit the structure of the substrate. However by changing the parameters of the CVD process, a polycrystalline layer of silicon may also be deposited. The deposition rate is ~1 to 2 μm/minute. When the CVD process is done at low pressure, it is called LPCVD. However, if it is done at atmospheric pressure, such as for depositing silicon dioxide, it is called APCVD. Gases of tri– or tetra–valent atoms such as diborane (B2H6) or phosphine (PH3) are added to the precursor gas mixture to do p– or n–type doping of the layer under growth by CVD process.
SiCl4 + H2→SiCl2 + 2HCl ; 2 SiCl2→Si + SiCl4
The deposited layer may inherit the structure of the substrate. However by changing the parameters of the CVD process, a polycrystalline layer of silicon may also be deposited. The deposition rate is ~1 to 2 μm/minute. When the CVD process is done at low pressure, it is called LPCVD. However, if it is done at atmospheric pressure, such as for depositing silicon dioxide, it is called APCVD. Gases of tri– or tetra–valent atoms such as diborane (B2H6) or phosphine (PH3) are added to the precursor gas mixture to do p– or n–type doping of the layer under growth by CVD process.
Photolithography: It is the process of transferring geometric shapes from a mask to a
layer or substrate via a film of photoresist. Mask is a quartz plate on which the designed
patterns of chrome have been created very precisely. The steps involved in the process
of photolithography are: wafer cleaning; barrier layer formation; photoresist application;
soft baking; mask alignment; exposure, development; and hard-baking.
On a chemically cleaned surface of the wafer, a polymer called photoresist is spun coated and baked at 90oC. Photoresist is an organic suspension that is sensitive to the ultraviolet radiation; exposure to the later changes its solubility in its designated developer. The next step in the photolithography process is mask alignment. In this critical step, a mask with chrome-patterns is placed over the photoresist coated oxidized wafer shown in the left diagram below. Now a wide beam of UV is transmitted through the mask onto the wafer.
While chrome patterns are opaque, quartz is transparent to the UV. So the pattern in the mask is transferred to the photoresist. If the photoresist is positive, Its UV exposed regions dissolve in the developer (as shown in the left column of the right diagram above). But if the photoresist is –ve, its UV exposed regions become insoluble in its own developer, whereas the unexposed regions would dissolve out. Once this exposed photoresist is developed, the wafer gets a patterned photoresist on its top. If it is hard baked at 120oC,
On a chemically cleaned surface of the wafer, a polymer called photoresist is spun coated and baked at 90oC. Photoresist is an organic suspension that is sensitive to the ultraviolet radiation; exposure to the later changes its solubility in its designated developer. The next step in the photolithography process is mask alignment. In this critical step, a mask with chrome-patterns is placed over the photoresist coated oxidized wafer shown in the left diagram below. Now a wide beam of UV is transmitted through the mask onto the wafer.
While chrome patterns are opaque, quartz is transparent to the UV. So the pattern in the mask is transferred to the photoresist. If the photoresist is positive, Its UV exposed regions dissolve in the developer (as shown in the left column of the right diagram above). But if the photoresist is –ve, its UV exposed regions become insoluble in its own developer, whereas the unexposed regions would dissolve out. Once this exposed photoresist is developed, the wafer gets a patterned photoresist on its top. If it is hard baked at 120oC,
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